i4 p6 Guest Editors’ Introduction: Promises and Challenges of Novel Interconnect Technologies

COMMERCIAL DESIGNS currently integrate tens to
hundreds of embedded functional and storage blocks
in a monolithic SoC, and the number is expected to
increase significantly in the near future.

With the well-known trend of continued CMOS
scaling in accordance with Moore’s law, it’s projected
that traditional on-chip interconnect systems will
soon be very limited in meeting the performance
needs and specifications of ICs and SoCs.

The conventional 2D copper-based IC is inherently
limited because of the planar structure’s geometrical
constraints.
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In ‘‘Carbon Nanomaterials: The Ideal Interconnect
Technology for Next-Generation ICs,’’ Hong Li, Chuan
Xu, and Kaustav Banerjee present a comprehensive
overview of state-of-the-art carbon nanomaterials
carbon nanotubes (CNTs) and graphene nanoribbons
(GNRs), as next-generation interconnect technology.

The next article is ‘‘Short-Range, Wireless Interconnect
within a Computing Chassis: Design Challenges,’’
by Patrick Chiang et al.

The fourth article, ‘‘Wireless Interconnect and the
Potential for Carbon Nanotubes’’ by Alireza Nojeh
and Andre Ivanov, explores the possibility of creating
an on-chip wireless communication network using
CNT antennas.

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