i4 p10 Optical Interconnect for High-End Computer Systems

RECENT ADVANCES IN silicon photonic technologies
offer the potential of closely integrated optical
communication and VLSI computation

Scaling: Background

(page 2)
Figure 1 raises a natural question: how do we maintain this performance curve?

Thus, gate delay and gates per clock, whose product
gives clock frequency, appear to scale either flatly
or minimally: less than 40% per generation, or 13%
per year.

However, continued scaling of Moore’s law
appears to be in jeopardy: partly because dimensions
are rapidly approaching atomic size, and atoms do
not scale, but mostly because global economic realities
will increasingly limit financial investment into the semiconductor market.

Multichip packages using optics

i4 p6 Guest Editors’ Introduction: Promises and Challenges of Novel Interconnect Technologies

COMMERCIAL DESIGNS currently integrate tens to
hundreds of embedded functional and storage blocks
in a monolithic SoC, and the number is expected to
increase significantly in the near future.

With the well-known trend of continued CMOS
scaling in accordance with Moore’s law, it’s projected
that traditional on-chip interconnect systems will
soon be very limited in meeting the performance
needs and specifications of ICs and SoCs.

The conventional 2D copper-based IC is inherently
limited because of the planar structure’s geometrical
constraints.
(page 1 col 2)
(page 2)
In ‘‘Carbon Nanomaterials: The Ideal Interconnect
Technology for Next-Generation ICs,’’ Hong Li, Chuan
Xu, and Kaustav Banerjee present a comprehensive
overview of state-of-the-art carbon nanomaterials
carbon nanotubes (CNTs) and graphene nanoribbons
(GNRs), as next-generation interconnect technology.

The next article is ‘‘Short-Range, Wireless Interconnect
within a Computing Chassis: Design Challenges,’’
by Patrick Chiang et al.

The fourth article, ‘‘Wireless Interconnect and the
Potential for Carbon Nanotubes’’ by Alireza Nojeh
and Andre Ivanov, explores the possibility of creating
an on-chip wireless communication network using
CNT antennas.

(pag 2 col 2)

i4 p4 Overcoming interconnect bottlenecks in gigascale ICs

INTERCONNECT COMPLEXITY is a serious problem for
nanoscale ICs today, and this problemwill only become
worse as we continue to scale devices and integrate
more transistors on a chip.

Recent special issues of IEEE Design & Test of Computers
have highlighted some of these solutions: for example,
3D integrated circuits, globally asynchronous
and locally synchronous (GALS) systems, and network-
on-chip.

This timely special issue responds to this challenge
by highlighting emerging and revolutionary interconnect
technologies that can dramatically transform the
way we design and fabricate ICs.

In addition to demonstrating high bandwidth, low
latency, and lower consumption, experts also discuss
issues of fault tolerance and manufacturability