Tuesday, August 31, 2010

i4 p4 Overcoming interconnect bottlenecks in gigascale ICs

INTERCONNECT COMPLEXITY is a serious problem for
nanoscale ICs today, and this problemwill only become
worse as we continue to scale devices and integrate
more transistors on a chip.

Recent special issues of IEEE Design & Test of Computers
have highlighted some of these solutions: for example,
3D integrated circuits, globally asynchronous
and locally synchronous (GALS) systems, and network-
on-chip.

This timely special issue responds to this challenge
by highlighting emerging and revolutionary interconnect
technologies that can dramatically transform the
way we design and fabricate ICs.

In addition to demonstrating high bandwidth, low
latency, and lower consumption, experts also discuss
issues of fault tolerance and manufacturability